Intel’s ‘Diamond Rapids’ Xeon 7 CPUs Reveal Distinct CBB & IMH Design
Recent patch notes detailing Intel’s upcoming ‘Diamond Rapids’ Xeon 7 processor family have unveiled key architectural differences compared to the preceding ‘Sapphire Rapids’. Notably, the new generation employs a segmented approach with separate Integrated I/O and Memory Hub (IMH) dies alongside the Compute Building Block (CBB) dies, utilizing distinct discovery tables for each.
The shift in design represents an evolution from previous Intel server CPU architectures. Traditionally, Intel’s CPUs have relied on a more unified approach to managing core resources and external interfaces. However, ‘Diamond Rapids’ appears to adopt a modular strategy, potentially offering greater flexibility and scalability for demanding server workloads.
Key Architectural Changes
- Separated Dies: The core distinction lies in the physical separation of the Compute Building Block (CBB) dies – responsible for processing operations – from the Integrated I/O and Memory Hub (IMH) dies. This division allows for independent management and optimization of these critical components.
- Distinct Discovery Tables: Each die type utilizes its own dedicated discovery table, streamlining communication and reducing potential bottlenecks within the system. This targeted approach contrasts with previous generations’ reliance on a single global discovery table portal.
- PMON Expansion: Intel has significantly expanded the number of Performance Monitor (PMON) types supported by ‘Diamond Rapids.’ This includes support for PCIe 6.0 – a relatively new standard initially slated for launch in late 2023 – further enhancing monitoring capabilities and potentially enabling optimized performance tuning.
- PCIe 6.0 Support: The inclusion of PCIe 6.0 offers a substantial bandwidth upgrade, crucial for accelerating data transfer rates within high-performance servers and workstations.
Lineup Adjustments & Channel Configuration
Initial reports indicated a streamlined product lineup for ‘Diamond Rapids’, with 8-channel variants being initially cut in favor of 16-channel SKUs. This shift towards 16-channel configurations is now the foundation of the entire family, suggesting a strategic focus on supporting demanding workloads that require increased memory bandwidth.
This change reflects Intel’s assessment of market needs and performance requirements within the server segment.
Analyst InstLatX64 has highlighted these developments, characterizing them as ‘insightful’ additions to the Linux kernel patch updates. Their observations reinforce the significance of the segmented die design and the expanded PMON capabilities.
The ‘Diamond Rapids’ Xeon 7 family is expected to launch later this year, marking a continued evolution in Intel’s server CPU strategy. The architectural refinements—particularly the separation of CBB and IMH dies—are likely to contribute to improved performance and efficiency across a range of applications, from data centers to high-performance computing.
Further developments and detailed specifications will be revealed as the launch date approaches.
