Thursday, March 12th 2026 Imec Launches University Consortium Around Next Generation of Chips Press Release by Nomad76 Today, 10:53 Discuss (0 ) Imec, a world-leading research and innovation hub in advanced semiconductor technologies, has launched a first of its kind consortium with 26 European university groups that will jointly work on the technology roadmap beyond CMOS scaling (CMOS 2.0). This initiative will focus on design automation and chip architecture research for the next generation of chips. The consortium will benefit from the NanoIC pilot line, turning academic insights into industry-focused innovations. In the future, similar consortia will be set up around advanced materials and alternative compute systems. CMOS 2.0 refers to a new paradigm, introduced by imec, that expands the chip making toolbox beyond traditional transistor scaling and its associated scaling challenges. CMOS 2.0 allows for more design flexibility by exploiting fine-grain wafer stacking technology to improve on-chip connectivity and offer higher technology heterogeneity to the system. It will result in tailored chips comprising multiple 3D-stacked layers that fulfil smartly partitioned functions. In that way, CMOS 2.0 will provide advanced, versatile 3D stacked platforms that push the boundaries of compute performance. Introducing this new paradigm will have profound implications on how computing architectures are designed and optimized for future workloads and applications. CMOS 2.0 is a key differentiator for the realization of next-generation energy efficient compute systems and is expected to impact a wide variety of applications from general purpose processors to High Performance AI Computing systems and even further for embedded AI applications at the edge. This strategically important research requires cross-pollination between different areas of the ecosystem. Within imec's CMOS 2.0-consortium, 26 PhDs will be funded. The PhD students will stay at their home university, embedded in their research group, allowing them to tap into complementary fields of expertise and stimulate cross-fertilization. The participating universities and imec will jointly develop the necessary know-how that lays down the foundation of the next generation CMOS technology platforms and their associated compute architectures. Moreover, the collaboration will support workforce and skill development in Europe to meet current and future industry needs.Sahar Sahhaf, Director Academic Partnership DevelopmentThe attraction for the concept of CMOS 2.0 is clear, but the obstacles are equally substantial. Leveraging the benefits in both connectivity and heterogeneous integration enabled by 3D wafer stacking will reshape every stage of design and chip architecture. It requires convergence of expertise, close collaboration, and coordination. It's the first time that imec brings together such a network of premium European university teams in a structured way to have guided contributions to the future semiconductor roadmap. We are excited to further connect academic inputs in our industry-driven programs to put Europe in the forefront of research on advanced computing technologies."Mehdi Tahoori, Technical DirectorThis university research consortium aims to infuse CMOS 2.0 technology to the entire design stack, from Electronic Design Automation (EDA) all the way to system architecture. It aims to stimulate the broader research and academic community on various aspects of the CMOS 2.0 revolution. Imec plays a unique and crucial role by linking academic research to industry needs, and by extending the roadmap of technology scaling with CMOS 2.0.Of particular importance is the presence of the NanoIC pilot line hosted by imec in Leuven and its decisive role in empowering the CMOS 2.0 academic consortium. Its state‑of‑the‑art tools are embedded within a strong, collaborative ecosystem of industry partners. PhD students can gain early exposure to next-generation semiconductor logic, memory and 3D technologies through process design kits (PDKs), which will enable them to develop system‑level thinking; which is typically only encountered much later in a research or industrial career. As such, it bridges the gap from academia to industry, facilitating a rapid transfer of knowledge and advanced technology from research labs to the market, thus strengthening Europe's industry. The CMOS 2.0 university consortium consists of following universities:National Technical University of AthensDelft University of TechnologyÉcole Polytechnique Fédérale de Lausanne (EPFL)Eidgenössische Technische Hochschule ZürichKarlsruhe Institute of TechnologyKatholieke Universiteit LeuvenKTH Royal Institute of TechnologyLIRMM, University of Montpellier, CNRSPolitecnico di TorinoSabancı UniversityUniversidad Complutense de MadridUniversiteit GentUniversité libre de BruxellesUniversity of Thessaly Source: Imec Related News Tags: academia chip CMOS development Electronic Design Automation Europe Imec next generation partners Research Technology Jul 25th 2025 Intel CEO Confirms SMT To Return to Future CPUs (95) Feb 8th 2026 30,000 NVIDIA Engineers Use Generative AI for 3x Higher Code Output (147) Mar 6th 2026 Imec Partners with Atlas to Develop Permanent DNA-Based Data Storage Technology (14) Feb 4th 2026 Western Digital Designs High-Bandwidth HDDs That Quadruple I/O Speeds (27) Mar 2nd 2026 NanoIC Launches Advanced Interconnect PDKs for Chip-to-Chip Designs (0) Feb 5th 2026 Forge Nano Transforms Advanced Semiconductor Chip Manufacturing with High-Speed 1000:1 Aspect Ratio Atomic Layer Deposition Coatings (1) Mar 10th 2026 IBM and Lam Research Announce Collaboration to Advance Sub-1 nm Logic Scaling (1) Feb 27th 2026 Broadcom Ships Industry First 2 nm Custom Compute SoC Built on Its 3.5D eXtreme Dimension System in Package Platform (1) Mar 11th 2026 Applied Materials and Micron Partner to Accelerate HBM, NAND and DRAM Development (1) Dec 24th 2025 NVIDIA Tested Intel's 18A Node but Did Not Commit to Intel Foundry (14) Add your own on Imec Launches University Consortium Around Next Generation of Chips There are no yet.
