Semiconductor scaling has entered uncharted territory. While the industry continues to shrink transistor dimensions, the transition from planar to three-dimensional structures is introducing a new layer of complexity at sub-1 nanometer nodes. IBM and Lam Research are expanding their long-standing collaboration to tackle these challenges head-on, with a focus on materials innovation, advanced lithography, and process integration that could redefine the future of chip manufacturing.
This latest phase of the partnership will concentrate on developing solutions for nodes below 1 nanometer, building upon proven advancements in 7 nanometer, nanosheet, and 2 nanometer technologies. The five-year agreement will leverage IBM’s expertise in materials science and process development—particularly at its Albany NanoTech Complex—alongside Lam Research’s portfolio of cutting-edge etch, deposition, and packaging tools. Key technologies like Aether dry resist, Kiyo etch platform, and Striker deposition system are expected to play crucial roles in enabling reliable pattern transfer for next-generation devices.
- At a glance:
- - Focus on sub-1 nanometer logic nodes with 3D architectures
- - Integration of High-NA EUV lithography for finer feature definition
- - Advanced materials and etch processes to improve yield and performance
- - Potential impact on AI workloads and high-performance computing
The shift to three-dimensional transistor designs—such as nanosheets and nanostacks—represents a fundamental change in how chips are manufactured. Unlike traditional planar scaling, these structures require new approaches to etching, deposition, and power delivery. Lam’s Kiyo platform, for example, is specifically engineered to handle the extreme aspect ratios needed for backside power delivery in 3D devices, while IBM’s research will validate full process flows from materials development to final integration.
High-NA EUV lithography remains a cornerstone of this effort. While competitors like ASML have already achieved 1,000-watt EUV power levels, the material and etch challenges at sub-1 nanometer nodes remain unresolved. IBM and Lam Research’s approach differentiates itself by addressing the entire process stack, from materials to lithography, rather than focusing on incremental improvements. This end-to-end development strategy could accelerate the commercialization of these advanced nodes, though significant engineering hurdles—including cost, yield, and integration—must still be overcome.
The potential impact on gaming and high-performance computing is substantial. Sub-1 nanometer scaling could enable transistors with lower power consumption and higher performance, which would be critical for AI workloads and next-generation gaming platforms. However, the transition will not be immediate. High-NA EUV lithography, while promising, introduces its own set of complexities that must be resolved before it can become mainstream.
This collaboration marks a pivotal moment in semiconductor technology. By focusing on 3D architectures and advanced materials, IBM and Lam Research are not just pushing the limits of scaling but redefining how chips are built. The success of this effort will determine whether the industry can continue to deliver performance gains while navigating the physical constraints of sub-1 nanometer manufacturing.
